搜索资源列表
Use-lab2-ISE-software
- 熟悉掌握VerilogHDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、 调试、仿真-Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for input, editing, debugging, simulation
verilog-ethernet-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-image-decompressor-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-uart-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
clk_div3
- 基于XIlinx ISE,用Verilog语言实现3分频电路,适合初学者-Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners
readmemb_verilog
- 自己总结的,在ise中verilog编程时需要注意的一些细节,主要是readmemb函数用法-Their own summary, in the ise verilog programming need to pay attention to some of the details, mainly readmemb function usage
costas-loop-in-ISE
- ISE软件中实现costas环的方案,使用语言为verilog。文件为word形式,不含有源代码,只包含实现过程及注意事项。-ISE COSTAS LOOP
ip核
- 购买的beckoff公司的ip核,提供了详细的datasheet以及协议说明,附上调用ip核的文件,采用verilog编写,平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol descr iption, attached to the ip kernel file, using verilog prepared, the platform can be set
RS
- 本文设计了基于FPGA的,用verilog HDL语言描述的在伽罗华域GF( )上的RS(6,4)编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述,然后在软件上进行编译、仿真,最终实现RS(6,4)编码,下载之后用chipscope采集数据,分析符合仿真结果,达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS
黑金Sparten6开发板Verilog教程V1.6
- 黑金xilinx ise fpga verlog 教程(Black gold Xilinx, ise, FPGA, verlog tutorials)
div1_feng
- 用verilog实现除法的功能,其中可以实现整数的除法,并有小数的表示。(verilog divider function ise fpga frequency)
encode_cell
- ISE14.7平台,实现verilog的8b10b编解码。(verilog in ise for 8b10b decode and incode)
parallel_norflash_test
- ISE工程,并行nor flash的读、写、擦出,其中有个调用FIFO16-16的IP核,已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
ddr3_test
- ddr3相关代码和基于ISE仿真调试,板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
Buzzer
- 采用verilo语言编写的蜂鸣器,可用ISE软件来试实现(Buzzer written in verilo language, available ISE software to try to achieve)
35_OV7725_VGA_DDR3_LX16_joint
- 多目摄像头同屏显示,实现图像分割,xilinx公司芯片,ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
RISC_CPU完整代码
- 硬件实现一个完整的CPU,利用verilog编写,可在ISE上直接使用(Hardware implements a full CPU)
14_ethernet_test
- 千兆网学习代码 ISE,状态机实现数据打包,基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现,ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)
04_led_test
- Verilog写的led灯,可用Vivado/ISE仿真平台仿真(Progress is not created by contented people.)